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TDA7348
DIGITALLY CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEW
INPUT MULTIPLEXER - THREE STEREO AND ONE MONO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES VOLUME CONTROL IN 0.3dB STEPS INCLUDING GAIN UP TO 20dB ZERO CROSSING MUTE AND DIRECT MUTE PAUSE DETECTOR WITH PROGRAMMABLE THRESHOLD SOFT MUTE CONTROLLED BY SOFTWARE OR HARDWARE PIN BASS AND TREBLE CONTROL FOUR SPEAKER ATTENUATORS - FOUR INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DESCRIPTION The TDA7348 is an upgrade of the TDA7318 audioprocessor. Thanks to the used BIPOLAR/CMOS technology, very low distortion, low noise and DC-stepping are obtained.
DIP28
SO28
ORDERING NUMBER: TDA7348 (DIP28) TDA7348D (SO28)
Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained Several new features like softmute, zero-crossing mute and pause detector are implemented. The Soft Mute function can be activated in two ways: 1 Via serial bus (bit D0, Mute Byte) 2 Directly on pin 22 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology.
November 1994
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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C10 2.2F C14 100nF SM BOUT(L) 22 SPKR ATT 26 MUTE VOL 1, 2 BASS SPKR ATT 24 MUTE 28 INPUT SELECTOR + GAIN SOFT MUTE SERIAL BUS DECODER + LATCHES 27 SCL SDA BUS OUT LEFT REAR TREBLE OUT LEFT FRONT 19 18 4 BIN(L) C15 100nF TREBLE(L) C16 2.7nF R2 4.7K OUT(L) 17 16 IN(L) RB L1 L2 L3 L4 ZERO CROSS + MUTE R4 R3 R2 R1 ZERO CROSS + MUTE VOL 1, 2 BASS TREBLE MUTE SPKR ATT 25 OUT RIGHT FRONT SPKR ATT RB MUTE 1 CREF C8 C9 2.2F 10F OUT(R) IN(R) CSM 7 6 15 CSM C11 47nF R1 4.7K 21 20 BOUT(R) 5 BIN(R) C12 100nF TREBLE(R)
D93AU100A
TDA7348
BLOCK DIAGRAM
3x 1F
L1
14
C1
LEFT INPUTS
L2
13
C2
L3
12
C3
C4
11
3x 1F
R3
8
C7
R2
9
RIGHT INPUTS
C6
R1
10
C5
VS
2
23
SUPPLY
OUT RIGHT REAR
3
AGND
C13 2.7nF
TDA7348
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
PIN CONNECTION
CREF VS GND TREBLE L R IN(R) OUT(R) IN R3 IN R2 IN R1 AM MONO IN L3 IN L2 IN L1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D94AU099
28 27 26 25 24 23 22 21 20 19 18 17 16 15
SCL SDA OUT LF OUT RF OUT LR OUT RR SM BOUT(R) BIN(R) BOUT(L) BIN(L) OUT(L) IN(L) CSM
BUS INPUTS
BASS
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-pins DIP28 85 SO28 65 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Volume Control Treble Control 2dB step Bass Control 2dB step Fader and Balance Control 1.25dB step Input Gain 3.75dB step Mute Attenuation -78.45 -14 -10 -38.75 0 100 Parameter Min. 6 2.1 Typ. 9 2.6 0.01 106 100 20 +14 +18 0 11.25 0.08 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB dB
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TDA7348
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all controls flat (G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT SELECTOR
RI VCL SI RL GI MIN GI MAX Gstep eN VDC Input Resistance Clipping Level Input Separation Output Load Resistance Minimum Input Gain Maximum Input Gain Step Resolution Input Noise DC Steps 20Hz to 20 KHz unweighted Adiacent Gain Steps GIMIN to GIMAX d 0.3% 70 2.1 80 2 -0.75 10.25 2.75 0 11.25 3.75 2.3 1.5 3 10 0.75 12.25 4.75 100 2.6 100 130 K VRMS dB K dB dB dB V mV mV
VOLUME CONTROL (1 + 2)
RI GMAX AMAX ASTEPC ASTEPF EA Et VDC Input Resistance Maximum Gain Maximum Attenuation Step Resolution Coarse Attenuation Step Resolution Fine Attenuation Attenuation Set Error Tracking Error DC Steps Adiacent Attenuation Steps From 0dB to AMAX -3 0 0.5 (Only Volume 1) G = 20 to -20dB G = -20 to -58dB 0.5 0.11 -1.25 -3 35 18.75 50 20 78.45 1.25 0.31 0 2.0 0.51 1.25 2 2 3 5 21.25 K dB dB dB dB dB dB dB mV mV
ZERO CROSSING MUTE
VTH Zero Crossing Threshold (note 1) WIN = 11 WIN = 10 WIN = 01 WIN = 00 AMUTE VDC Mute Attenuation DC Step 0dB to Mute 80 20 40 80 160 100 0 3 mV mV mV mV dB mV
SOFT MUTE
AMUTE TDON TDOFF VTHSM RINT VSMH VSML Mute Attenuation ON Delay Time OFF Current Soft Mute Threshold Pullup Resistor (pin 22) (pin 22) Level High (pin 22) Level Low (note 2) Soft Mute Active CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN VCSM = 0V; I = IMAX VCSM = 0V; I = IMIN 1.5 35 3.5 1 45 0.7 20 25 60 1 35 50 1 2.5 50 3.5 65 1.7 55 75 dB ms ms A A V K V V
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TDA7348
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
BASS CONTROL
BBOOST BCUT Astep Rg Max Bass Boost Max Bass Cut Step Resolution Internal Feedback Resistance 15 -8.5 1 45 13 1 18 -10 2 65 14 2 20 -11.5 3 85 15 3 dB dB dB K
TREBLE CONTROL
CRANGE Astep Control Range Step Resolution dB dB
SPEAKER ATTENUATORS
CRANGE Astep AMUTE EA VDC Control Range Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Adjacent Attenuation Steps 0 Data Word = XXX11111 35 0.5 80 37.5 1.25 100 1.25 3 40 2.0 dB dB dB dB mV
AUDIO OUTPUT
Vclip RL RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level 3.5 d = 0.3% 2.1 2 30 3.8 100 4.1 2.6 Vrms K V
GENERAL
VCC ICC PSRR e NO Et S/N SC d Supply Voltage Supply Current Power Supply Rejection Ratio Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation Distortion VIN = 1V f = 1KHz B = 20 to 20kHz "A" weighted Output Muted (B = 20 to 20kHz flat) All Gains 0dB (B = 20 to 20kHz flat) AV = 0 to -20dB AV = -20 to -60dB All Gains = 0dB; VO = 1Vrms 80 60 6 9 10 80 65 2.5 5 0 0 106 100 0.01 0.08 15 1 2 10.2 15 V mA dB dB V V dB dB dB dB %
BUS INPUTS
VIL VlN IlN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 1 V V A V
Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold Note 2: Internal pullup resistor to Vs/2; "LOW" = softmute active r
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TDA7348
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7348 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
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TDA7348
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte,(the LSB bit determines read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB S 1 0 0 0 1 0
LSB
MSB X X I
LSB A3 A2 A1 A0 AC K
MSB DATA
LSB
AC P K
0 R/W AC X K
ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used
MAX CLOCK SPEED 500kbits/s
AUTO INCREMENT If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled SUBADDRESS (receive mode)
MSB X X X I A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 LSB A0 0 1 0 1 0 1 0 1 0 Input Selector Volume 2 Volume 1 Bass, Treble Speaker Attenuator LF Speaker Attenuator LR Speaker Attenuator RF Speaker Attenuator RR Mute FUNCTION
TRANSMITTED DATA Send Mode
MSB X X X X X SM ZM LSB X
ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chipaddress.
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TDA7348
DATA BYTE SPECIFICATION X = not relevant; set to "1" during testing Input Selector
MSB D7 X X X X X X X X X X X X D6 X X X X X X X X X X X X D5 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 not used IN 2 IN 1 AM mono not used IN 3 not allowed not allowed 11.25dB gain 7.5dB gain 3.75dB gain 0dB gain FUNCTION
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1 Volume 2
MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB -10dB -11.25dB -12.5dB -13.75dB -15dB -16.25dB -17.5dB -18.75dB
For example to select -17.5dB attenuation the Data Byte is: X X X1 1 1 1 0
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TDA7348
Mute
MSB D7 D6 D5 D4 D3 D2 D1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 LSB D0 1 1 1 Soft Mute On Soft Mute with fast slope (I = IMAX) Soft Mute with slow slope (I = IMIN) Direct Mute Zero Crossing Mute On Zero Crossing Mute Off (delayed until next zerocrossing) Zero Crossing Mute and Pause Detector Reset 160mV ZC Window Threshold (WIN = 00) 80mV ZC Window Threshold (WIN = 01) 40mV ZC Window Threshold (WIN = 10) 20mV ZC Window Threshold (WIN = 11) Nonsymmetrical Bass Cut (note 4) Symmetrical Bass Cut FUNCTION
An additional direct mute function is included in the Speaker Attenuators.
Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
Speaker Attenuators
MSB D7 X X X X X X X X X X X X X D6 X X X X X X X X X X X X X D5 X X X X X X X X X X X X X 0 0 1 1 1 0 1 0 1 1 1 1 1 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER ATTENUATOR LF, LR, RF, RR 1.25dB step 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB step 0dB -10dB -20dB -30dB Speaker Mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
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TDA7348
Bass/Treble
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 FUNCTION TREBLE STEP -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB BASS STEPS -10dB -8dB -6dB -4dB -2dB -0dB -0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 146B 18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
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TDA7348
Volume 1
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LSB D0 0 1 0 1 FUNCTION 0.31dB Fine Attenuation Steps 0dB -0.31dB -0.62dB -0.94dB 1.25dB Coarse Attenuation Steps 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB Gain / Attenuation Steps 20dB 10dB 0dB -10dB -20dB -30dB -40dB -50dB
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1 Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
Purchase of I2C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
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TDA7348
DIP28 PACKAGE MECHANICAL DATA
DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 33.02 14.1 0.175 0.130 0.23 1.27 37.34 16.68 0.598 0.100 1.300 0.555 mm TYP. 0.63 0.45 0.31 0.009 0.050 1.470 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
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TDA7348
SO28 PACKAGE MECHANICAL DATA
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 8 (max.) 0.291 0.016 18.1 10.65 0.1 0.35 0.23 0.5 45 (typ.) 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
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TDA7348
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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